Tanaka Teruo

Faculty of Informatics Department of Computer ScienceProfessor

  • E-Mail: terucc.kogakuin.ac.jp

    Career

    • Apr. 2023 - Present
      工学院大学
    • Sep. 2022 - Present
      アーク情報システムズ
    • Apr. 2011 - Present
      工学院大学大学院
    • Apr. 2020 - Mar. 2022
      工学院大学大学院
    • Apr. 2014 - Mar. 2020
      Kogakuin University, Faculty of Informatics, Department of Computer Science
    • Apr. 2012 - Mar. 2015
      工学院大学
    • Apr. 2011 - Present
      Kogakuin University, Faculty of Informatics, Department of Computer Science
    • Apr. 2007 - Mar. 2011
      (株)日立超LSIシステムズ
    • Apr. 2009 - Sep. 2009
      宮崎大学
    • Apr. 2004 - Mar. 2007
      Hitachi, Ltd.,
    • Oct. 1998 - Mar. 2005
      電気通信大学
    • Feb. 1996 - Mar. 2004
      Hitachi, Ltd.,
    • Apr. 1983 - Feb. 1996
      Hitachi, Ltd.,, Central Research Laboratory

    Educational Background

    • Apr. 2005 - Mar. 2007
      The University of Electro-Communications, Graduate School, Division of Information Systems
    • Apr. 1981 - Mar. 1983
      The University of Electro-Communications, Graduate School, Division of Electro Communications
    • Apr. 1977 - Mar. 1981
      The University of Electro-Communications, Faculty of Electro Communications

    Degree

    • Mar. 1981
      工学士, The University of Electro-Communications
    • Mar. 1983
      工学修士, The University of Electro-Communications
    • Mar. 2007
      博士(工学), The University of Electro-Communications

    Affiliated academic society

    • Aug. 2011 - Present
      IEEE Computer Society
    • Apr. 1990 - Present
      応用数理学会
    • Apr. 1981 - Present
      情報処理学会
    • IEEE Computer Society

    IDs

    • Identifiers

      研究者番号:90622837
      researchmap会員ID:5000096810
      J-Global ID:200901072916828097

    Research Field

    • Informatics, Computer systems, Computer System Network
    • Informatics, Information networks

    Research Keyword

    • Software Auto-tuning
    • Computer Architecture
    • Software Auto-tuning
    • Computer Architecture

    Paper

    • Light Weight Coarse Grid Aggregation for Smoothed Aggregation Algebraic Multigrid Solver
      Fujii; Akihiro and Tanaka; Teruo and Nakajima; Kengo
      IEEE ACCESS, 2024, [Reviewed]
      Lead
    • Parallelization of Automatic Tuning for Hyperparameter Optimization of Pedestrian Route Prediction Applications using Machine Learning
      Sorataro Fujika; Yuga Yajima; Teruo Tanaka; Akihiro Fujii; Yuka Kato; Satoshi Ohshima; Takahiro Katagiri
      HPC Asia '23: Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 27 Feb. 2023, [Reviewed]
    • Time Segment Correction Method for Parallel Time Integration
      Akihiro Fujii; Shigeo Kaneko; Teruo Tanaka; Takeshi Iwashita
      Journal of Information Processing, 15 Dec. 2019, [Reviewed]
      Lead
    • Acceleration of Symmetric Sparse Matrix-Vector Product using Improved Hierarchical Diagonal Blocking Format
      Ryo Muro; Akihiro Fujii; Teruo Tanaka
      International Conference on High Performance Computing in Asia-Pacific Region (HPCAsia 2019), Guangzhou, China, 16 Jan. 2019, [Reviewed]
    • ソフトウェア自動チューニングにおける複数同時性能パラメタ探索手法の提案と評価
      03 Aug. 2018, [Reviewed]
    • Strategy of Precision Switching for Mixed Precision Iterative Method
      Masaki Suwa; Akihiro Fujii; Teruo Tanaka; Hidehiko Hasegawa
      10th International Workshop on,Parallel Matrix Algorithms and Applications,(PMAA 18), 27 Jun. 2018, [Reviewed]
    • Algebraic Multigrid Solver using Coarse Grid Aggregation with Independent Aggregation
      Naoya Nomura; Akihiro Fujii; Teruo Tanaka; Osni Marques and Kengo Nakajima
      International Workshop on Automatic Performance Tuning (iWAPT2018), 25 May 2018, [Reviewed]
    • D-Spline Performance Tuning Method Flexibly Responsive to Execution Time Perturbation
      Guuing Fan; Masayoshi Mochizuki; Akihiro Fujii; Teruo Tanaka; Takahiro Katagiri
      12th International Conference on Parallel Processing and Applied Mathematics (PPAM2017), 12 Sep. 2017, [Reviewed]
    • Fast Multidimensional Performance Parameter Estimation with Multiple One-dimensional d-Spline Parameter Search
      Masayoshi Mochizuki; Akihiro Fujii; Teruo Tanaka; Takahiro Katagiri
      International Workshop on Automatic Performance Tuning (iWAPT2017), 02 Jun. 2017, [Reviewed]
    • 共役勾配法への種々の通信削減手法の適用と評価
      13 Jan. 2016, [Reviewed]
    • AVX2を用いた倍精度BCRS形式疎行列と倍々精度ベクトル積の高速化
      Sep. 2014, [Reviewed]
    • Implementation of d-Spline based Incremental Performance Parameter Estimation Method with ppOpen-AT
      Teruo Tanaka; Ryo Otsuka; Akihiro Fujii; Takahiro Katagiri; Toshiyuki Imamura
      Scientific Programming 2014, IOS Press, Jul. 2014, [Reviewed]

    MISC

    • Xev-GMP: Automatic code generation for GMP multiple-precisition code from C code
      Toshiaki Hishinuma; Takuma Sakakibara; Akihiro Fujii; Teruo Tanaka; Shiichi Hirasawa
      19th IEEE International Conference on Computational Science and Engineering (CSE 2016), 24 Aug. 2016
    • SIMD Parallel Sparse Matrix-Vector and Transposed-Matrix-Vector Multiplication in DD Precision
      Toshiaki Hishinuma; Hidehiko Hasegawa; Teruo Tanaka
      12th International Meeting High Performance Computing for Computational Science, VECPAR 2016, 24 Jun. 2016
    • Performance Analysis of SA-AMG Method by Setting Extracted Near-kernel Vectors
      Naoya Nomura; Akihiro Fujii; Teruo Tanaka; Kengo Nakajima; Osni Marques
      12th International Meeting High Performance Computing for Computational Science, VECPAR 2016, 24 Jun. 2016
    • Coarse grid aggregation for SA-AMG method with multiple kernel vectors
      Akihiro Fujii; Naoya Nomura; Teruo Tanaka; Kengo Nakajima; Osni Marques
      SIAM conference on Parallel Processing for Scientific Computing, Paris, France, 12 Apr. 2016
    • Enhancement of Incremental Performance Parameter Estimation on ppOpen-AT
      Riku Murata; Jun Irie; Akihiro Fujii; Teruo Tanaka; Takahiro Katagiri
      Special Session: Auto-Tuning for Multicore and GPU (ATMG-15) In Conjunction with the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-15), 24 Sep. 2015
    • Performance Analysis of the Chebyshev Basis Conjugate Gradient Method on the K Computer
      Yosuke Kumagai; Akihiro Fujii; Teruo Tanaka; Yusuke Hirota; Takeshi Fukaya; Toshiyuki Imamura; Reiji Suda
      11th International Conference on Parallel Processing and Applied Mathematics (PPAM2015), 07 Sep. 2015
    • Communication Optimization Technique of Algebraic multi-grid solver to Each Computing System
      Akihiro Fujii; Takuya Nomura; Teruo Tanaka
      IEEE 8th International Symposium on Embedded multicore/manycore SOCS (MCSoC), 23 Sep. 2014
    • Mixed-Precision AMG method for Many Core Accelerators
      Yuki Sumiyoshi; Akihiro Fujii; Akira Nukada; Teruo Tanaka
      EuroMPI/ASIA '14 Proceedings of the 21st European MPI Users' Group Meeting, 08 Sep. 2014
    • Fast computation of double precision sparse matrix in BCRS and DD vector product using AVX2
      Toshiaki Hishinuma; Akihiro Fujii; Teruo Tanaka; Hidehiko Hasegawa
      11th International Meeting High Performance Computing for Computational Science, VECPAR 2014, poster paper, 01 Jul. 2014
    • Strassen のアルゴリズムを用いた行列積自動チューニングライブラリ
      30 Mar. 2014, [Reviewed]
    • 疎行列ベクトル積に対する OpenMP スケジューリング方式の分析
      07 Jan. 2014
    • AVXacceleration of DD arithmetic between a sparse matrix and vector
      Toshiaki Hishinuma; Akihiro Fujii; Teruo Tanaka; Hidehiko Hasegawa
      10th International Conference on Parallel Processing and Applied Mathematics (PPAM2013), Workshop on Numerical Algorithms on Hybrid Architectures, Parallel Processing and Applied Mathematics, Lecture Notes in Computer Science, 11 Sep. 2013
    • Chebyshev Polynomial Smoother in Multiple GPU-based AMG method
      Yuki Araya; Akihiro Fujii; Teruo Tanaka
      Fourth International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies(HEART2013), P12, Poster Presentation, 11 Jun. 2013
    • マルチカラー法を用いたマルチGPU上でのAMG法
      30 Mar. 2013, [Reviewed]
    • Acceleration of Ant Colony Optimization for the Traveling Salesman Problem on a GPU
      Kazuta Kobashi; Akihiro Fujii; Teruo Tanaka; Kazunori Miyoshi
      Proceedings of the 23rd IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2011) , Track: 757-070, Dec. 2011
    • GPGPU-based Algebraic Multigrid Method
      Kosuke Takahashi; Akihiro Fujii; Teruo Tanaka
      Proceedings of the 23rd IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2011) , Track: 757-061, ACTA Press, Dec. 2011
    • d-Spline Based Incremental Parameter Estimation in Automatic Performance Tuning, Applied Parallel Computing, State of the Art in Scientific Computing
      T.Tanaka; T.Katagiri; T.Yuba
      Lecture Notes in Computer Science, Springer, Oct. 2007
    • ソフトウェア自動チューニングにおける標本点逐次追加型性能パラメタ推定法
      Apr. 2007, [Reviewed]
    • d-Spline Based Incremental Parameter Estimation in Automatic Performance Tuning, Applied Parallel Computing, State of the Art in Scientific Computing
      2007
    • d-Spline Based Incremental Parameter Estimation in Automatic Performance Tuning
      T.Tanaka; T.Katagiri; T.Yuba
      8th International Workshop, PARA‘06, Jun. 2006
    • 情報漏えいを阻止するセキュアクライアントソリューション
      May 2006
    • d-Spline Based Incremental Parameter Estimation in Automatic Performance Tuning
      T.Tanaka; T.Katagiri; T.Yuba
      8th International Workshop, PARA‘06, 2006
    • コアビジネスへの集中をサポートするプラットフォームソリューション
      Jun. 2004
    • Harmonious Computingを実現するサーバ製品
      Jul. 2003
    • Dynamic Gateways: A Novel Approach to Improve Networking Performance and Availability on Parallel Servers
      F.B.Maciel; N.Sagawa and T.Tanaka
      HPCN Europe‘98, Springer, Lecture Notes in Computer Science, Apr. 1998
    • Dynamic Gateways: A Novel Approach to Improve Networking Performance and Availability on Parallel Servers
      1998
    • Scalable Parallel Memory Architecture with a Skew Scheme
      T.Sakakibara; K.Kitai; T.Isobe; S.Yazawa; T.Tanaka; Y.Takami; Y; Inagami
      Transaction of IEICE, Sep. 1997, [Reviewed]
    • Interprocessor Memory Access Arbitrating Scheme for TCMP Type Vector Supercomputer
      T.Sakakibara; K.Kitai; T.Isobe; S.Yazawa; T.Tanaka; Y.Takami; Y; Inagami
      Transaction of IEICE, Sep. 1997, [Reviewed]
    • Deadlock-free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and its Implementation for the Hitachi SR2201
      T.Yasuda; H.Fujii; H.Akashi; Y.Inagami; T.Tanaka; J.Nakagoshi; H.Wada; T.Sumimoto
      Proceedings of IPPS‘97, Apr. 1997
    • Interprocessor Memory Access Arbitrating Scheme for TCMP Type Vector Supercomputer
      1997
    • Deadlock-free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and its Implementation for the Hitachi SR2201
      T.Yasuda; H.Fujii; H.Akashi; Y.Inagami; T.Tanaka; J.Nakagoshi; H.Wada; T.Sumimoto
      Proceedings of IPPS‘97, 1997
    • Scalable Parallel Memory Architecture with a Skew Scheme
      T.Sakakibara; K.Kitai; T.Isobe; S.Yazawa; T.Tanaka; Y.Takami; Y; Inagami
      Transaction of IEICE, 1997
    • Distributed Storage Control Unit for the Hitach S-3800 Multivector Supercomputer
      K.Kitai; T.Isobe; T.Sakakibara; S.Yazawa; Y.Tamaki; T.Tanaka; K.Ishii
      Proc. of ICS '94, Jun. 1994
    • Distributed Storage Control Unit for the Hitach S-3800 Multivector Supercomputer
      1994
    • An interprocessor memory access arbitrating scheme for the S-3800 vector supercomputer
      SAKAKIBARA T.
      Proc. of Int'l. Symp. on Parallel Architectures, Algorithms and Networks, 1994
    • An Interprocessor Memory Access Arbitrating Scheme for S-3800 Vector Supercomputer
      F.B.Maciel; N.Sagawa; T.Tanaka
      Proc. of International Symposium on Parallel Architecture, Algorithms and Networks, 1994
    • Scalable parallel memory architecture with a skew scheme
      SAKAKIBARA T.
      Proc. of Int'l Conf. on Supercomputing, 1993
    • Scalable Parallel Memory Architecture with a Skew Scheme
      K.Kitai; T.Isobe; T.Sakakibara; S.Yazawa; Y.Tamaki; T.Tanaka; K.Ishii
      Proc. of ICS '93, 1993
    • Reducing Network Hardware Quantity by Employing Multi-processor Cluster Structure in Distributed Memory Parallel Processor
      K.Kitai; T.Isobe; T.Sakakibara; S.Yazawa; Y.Tamaki; T.Tanaka; K.Ishii
      Proc. of CONPAR 92/VAPP V, Jun. 1992
    • Reducing Network Hardware Quantity by Employing Multi-processor Cluster Structure in Distributed Memory Parallel Processor
      1992
    • 高並列計算機向きCFDプログラムの並列化技法, 水島, 岡崎編乱流の統計理論と応用
      Feb. 1991
    • 高並列計算機による空気力学シミュレーションの構想
      Sep. 1990
    • ベイスの方法によるデータのあてはめ
      Mar. 1983

    Lectures, oral presentations, etc.

    • Acceleration Techniques for Software Auto-Tuning to Hyperparameters on Machine Learning Software
      Teruo Tanaka
      2024 Conference on Advanced Topics and Auto Tuning in High-Performance Scientific Computing (ATAT on HPSC), 22 Mar. 2024, ATAT on HPSC, [Invited]
    • コンピュータにおける専用と汎用について −PCSとGPUを用いた科学技術計算−
      15 Mar. 2024
    • OpenACCを用いた単精度LU 分解のGPU 並列化
      15 Mar. 2024
    • Job level parallel search in software auto-tuning
      Yuga Yajima; Akihiro Fujii; Teruo Tanaka
      International conference series on HPC technologies in Asia Pacific region (HPC Asia 2024), 26 Jan. 2024
    • Fast adjacent communication among with RDMA
      Kota Yoshimoto; Akihiro Fujii; Teruo Tanaka
      International conference series on HPC technologies in Asia Pacific region (HPC Asia 2024), 26 Jan. 2024
    • 機械学習ソフトウェアへのソフトウェア自動チューニングの適用
      27 Oct. 2023
    • SA-AMG法における反復行列を用いたニアカーネル成分の設定手法の評価
      16 Mar. 2023
    • TSC Method using Semi-Implicit Method for Spring Mass Simulation
      Ryo Sagayama; Akihiro Fujii; Teruo Tanaka; Takumi Washio; Takeshi Iwashita
      HPCAsia2023, 01 Mar. 2023
    • Applying Automatic Tuning to Hyper-parameter Optimization of Machine Learning Programs for Super-Resolution
      Xuan Yang; Sorataro Fujika; Yuga Yajima; Akihiro Fujii; Teruo Tanaka; Kazutoshi Akita; Norimichi Ukita; Satoshi Ohshima
      International conference series on HPC technologies in Asia Pacific region (HPC Asia 2023), 01 Mar. 2023
    • 機械学習ソフトウェアへのソフトウェア自動チューニング技術の適用
      07 Jul. 2022
    • FX1000におけるダブルバッファリングとRDMAを用いた隣接通信の性能評価
      01 Jun. 2022
    • 超解像のための機械学習プログラムのハイパーパラメタ最適化に対する自動チューニングの適用
      11 May 2022
    • ディレクティブベースのGPUプログラミングモデルを用いた倍々精度演算の性能評価
      04 Mar. 2022
    • 倍々精度演算におけるSIMD命令利用時のデータレイアウトによる性能差分析
      04 Mar. 2022
    • “写しとしてのコンピュータ” KOPACの技術史的意義について
      04 Mar. 2022
    • ソフトウェア自動チューニングツール DSICE の構築
      03 Mar. 2022
    • ソフトウェア自動チューニングにおける反復1次元d-spline探索法の複数か所同時適用
      03 Mar. 2022
    • 複数のGPU 向けプログラミングモデルを用いた倍々精度疎行列ベクトル積の特性分析
      02 Mar. 2023
    • 慈道亮人,寺田洋人,菱沼利彰,藤井昭宏,田中輝雄
      02 Mar. 2023
    • 統計機と電子計算機の転換期に見るコンピュータらしさに関する考察
      02 Mar. 2023
    • RDMA with Double Buffering for Adjacent Communication
      Kota Yoshimoto; Akihiro Fujii; Teruo Tanaka
      International conference series on HPC technologies in Asia Pacific region (HPC Asia 2022), 14 Jan. 2022
    • Parallelization of Automatic Tuning by Executing ,Machine Learning Programs in Multiple Jobs
      Sorataro Fujika; Teruo Tanaka; Akihiro Fujii; Yuka Kato; Satoshi Ohshima; Takahiro Katagiri
      International conference series on HPC technologies in Asia Pacific region (HPC Asia 2022), 12 Jan. 2022
    • Parallelization of Automatic Tuning using Multiple Jobs for Machine Learning Programs
      Sorataro Fujika; Teruo Tanaka; Akihiro Fujii; Yuka Kato; Satoshi Ohshima; Takahiro Katagiri
      The 20th International Symposium on Advanced Technology (ISAT-20), 23 Nov. 2021
    • Fast Adjacent Communication with RDMA and Double Buffering
      Kota Yoshimoto; Akihiro Fujii; Teruo Tanaka
      The 20th International Symposium on Advanced Technology (ISAT-20), 23 Nov. 2021
    • SA-AMG法における軽量な粗格子集約手法と富岳上でのウィークスケーリング性能評価
      27 Sep. 2021
    • 不老上での自動チューニング機構の並列化と機械学習プログラムに適用時の安定性の検証
      13 Aug. 2021
    • 機械学習ソフトウェアへのソフトウェア自動チューニング技術の適用
      09 Jul. 2021
    • ばね質点シミュレーションに対するTSC法の有効性の検証
      26 May 2021
    • マルチGPU環境における機械学習ハイパーパラメータの自動チューニング(2)
      18 Mar. 2021
    • マルチGPU環境における機械学習ハイパーパラメータの自動チューニング(1)
      18 Mar. 2021
    • GPUクラスタを用いて並列化した自動チューニングの機械学習プログラムへの適用と安定性の検証
      16 Mar. 2021
    • Intel Xeonプロセッサ上におけるAVX512を用いた倍々精度演算の性能評価
      08 Sep. 2020
    • 複数のパラメータを同時に推定する手,法の実装と機械学習ソフトウェアへの適用
      10 Jun. 2020
    • Stable Automatic Tuning Method for Performance Fluctuation
      Naoto Seki; Toshiki Tabeta; Akihiro Fujii; Teruo Tanaka
      2020 SIAM Conference on Computational Science and Engineering, 12 Feb. 2020
    • An Optimization Technology of Software Auto-Tuning Applied to Machine Learning Software
      Toshiki Tabeta; Naoto Seki; Akihiro Fujii; Teruo Tanaka; Hiroyuki Takizawa
      International conference series on HPC technologies in Asia Pacific region (HPC Asia 2020), 15 Jan. 2020
    • Block Multicolor Gauss-Seidelにおけるブロッキングとカラーリングの影響分析
      Dec. 2019
    • 性能パラメータ推定における評価対象プログラムの実行時間の揺らぎに対応した自動チューニング手法の提案
      May 2019
    • Multigrid Reduction in Time preconditioning for parallel-in-time Krylov solver
      Ryo Yoda; Akihiro Fujii; Teruo Tanaka
      2019 Copper Mountain Conference on Multigrid Methods, CopperMountain, Colorado, 26 Mar. 2019
    • Space-Filling Curves(SFC)を用いた領域分割の性能評価
      16 Mar. 2019
    • MASツールを用いたTSPにおける量子アニーリングプログラムの挙動解析
      16 Mar. 2019
    • ソフトウェア自動チューニングにおける複数性能パラメータを同時推定する手法の効率化
      16 Mar. 2019
    • GPU上の線形ソルバにおける高速化と評価
      15 Mar. 2019
    • GPUを用いた行列-行列積の実装と性能評価
      15 Mar. 2019
    • 共役勾配法におけるダブルバッファリング利用したRDMA通信の性能評価
      15 Mar. 2019
    • ソフトウェア自動チューニングにおける反復2次元d-Spline探索法の提案と評価
      06 Mar. 2019
    • A Parallel Time Integration Approach without Re-discretization in Time Direction
      Akihiro Fujii; Teruo Tanaka
      2019 SIAM Conference on Computational Science and Engineering, 27 Feb. 2019
    • Evaluation of Time segmented correction method for parallel time integration
      Akihiro Fujii; Shigeo Kaneko; Teruo Tanaka; Takeshi Iwashita
      2019 Conference on Advanced Topics and Auto Tuning in High-Performance Scientific Computing (ATAT in HPSC 2019), 15 Feb. 2019
    • Enhancement of Performance Parameter Search Method for Multiple Parameter Estimation
      Teruo Tanaka; Fan Guuing; Akihiro Fujii; Takahiro Katagiri
      2019 Conference on Advanced Topics and Auto Tuning in High-Performance Scientific Computing (ATAT in HPSC 2019), 15 Feb. 2019
    • pp-OpenAT上の自動チューニング機構の実装
      31 Aug. 2018
    • Chebyshev基底通信削減CG法のマルチコア・メニーコア計算環境における性能評価
      01 Aug. 2018
    • 複数性能パラメタに対する低コスト実行時自動チューニング
      07 Jun. 2018
    • Low Cost Multiple One-dimensional d-Spline Parameter Search for Multiple Performance Parameter Estimation
      Teruo Tanaka; Masayoshi Mochizuki; Akihiro Fujii; Takahiro Katagiri
      2018 Conference on Advanced Topics and Auto Tuning in High-Performance Scientific Computing (ATAT in HPSC 2018), 27 Mar. 2018
    • Acceleration of sparse linear solvers using RDMA communication on PRIMEHPC FX supercomputer
      Akihiro Fujii; Teruo Tanaka; Takahiro Katagiri
      2018 Conference on Advanced Topics and Auto Tuning in High-Performance Scientific Computing (ATAT in HPSC 2018), 27 Mar. 2018
    • Latin Hypercube Designの3次元空間への拡張
      13 Mar. 2018
    • ソフトウェア自動チューニングにおける反復一次元探索による複数性能パラメータ推定法の実装と評価
      13 Mar. 2018
    • 粒子法における空間充填曲線を利用したハイブリッド並列化
      13 Mar. 2018
    • Intel/KNLにおける倍々精度疎行列ベクトル積の特性評価
      13 Mar. 2018
    • Consideration on the Optimal Balance Between Space Parallelism and Time Parallelism
      Ryo Yoda; Akihiro Fujii; Teruo Tanaka; Kengo Nakajima
      SIAM Conference on Parallel Processing for Scientific Computing, 08 Mar. 2018
    • 空間並列度および時間並列度の割り当て方に対する考察
      02 Mar. 2018
    • Hierarchical Diagonal Blocking形式における疎行列ベクトル積の高速化
      18 Dec. 2017
    • 複数ばねによる質点の一次元運動シミュレーションに対するMultigrid Reduction in Timeの有効性の評価
      18 Dec. 2017
    • Comparison of Correction Method in Parallelization in Time Direction -MGRIT and TSC-
      Shigeo Kaneko; Hiroki Fujito; Akihiro Fujii; Teruo Tanaka; Takeshi Iwashita
      The 16th International Symposium on Advanced Technology (ISAT-16), 02 Nov. 2017
    • Evaluation of Four-dimensional Performance Parameter Search by Iterative One-dimensional d-Spline Search
      Masayoshi Mochizuki; Guuing Fan; Akihiro Fujii; Teruo Tanaka
      The 16th International Symposium on Advanced Technology (ISAT-16), 02 Nov. 2017
    • 非線形熱拡散方程式を対象とした時間方向の並列化手法における補正手法の比較ーMGRITとTSC-
      20 Sep. 2017
    • 複数性能パラメタによる自動チューニングにおける性能パラメタ間相関関係の影響
      06 Sep. 2017
    • 反復線形探索による複数性能パラメタの自動チューニング
      05 Jun. 2017
    • Impact of RDMA communication for sparse linear solvers on FX10
      Akihiro Fujii; Teruo Tanaka
      30th Advanced Supercomputing Environment (ASE) Seminar (Ode to Multigrid), 31 May 2017, Supercomputing Division, Information Technology Center, The University of Tokyo
    • ATMathCoreLibを用いた代数的多重格子法の階層的パラメタ最適化
      31 May 2017
    • Performance Analysis of SA-AMG Solver with Additional Near-Kernel Vectors at Coarser Levels
      Naoya Nomura; Akihiro Fujii; Teruo Tanaka; Kengo Nakajima; Osni Marques
      18th Copper Mountain Conference on Multigrid Methods, Copper Mountain, Colorado, United States, 28 Mar. 2017
    • Xev-GMPへのMPI通信機能の拡張と反復解法への適用に向けた評価
      27 Mar. 2017
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      N.Hamanaka; T.Tanaka; K.Omoda; S.Nagashima
    • 2564264, 昭61-267174, 昭60-108116, 2564264 ベクトル処理方法およびベクトルプロセッサ
    • US5530881, US5530881 Vector processing apparatus for processing different instruction set architectures corresponding to mingled-type programs and separate-type programs
      Y.Inagami; S.Nagasima; K.Omoda; T.Nakagwa; T.Tanaka
    • US5517619, US5517619 Interconnection network and crossbar switch for the same
      A.Muramatsu; K.Sakoda; I.Yoshihara; K.Nakao; M.Nohmi; N.Hamanaka; S.Nagashima; T.Tanaka
    • US5506980, US5506980Method and apparatus for parallel processing of a large data array utilizing a shared auxiliary memory
      Y.Inagami; S.Nagasima; K.Omoda; T.Nakagwa; T.Tanaka
    • 平07-107680, 昭63-104166, 昭61-255663, H07-107680 並列プロセッサのプロセッサ間データ転送装置
    • US5465380, EP0255857, US5465380, EP0255857 Data transfer method of transferring data between programs of a same program group in different processors using unique identifiers of the programs
      N.Hamanaka; T.Tanaka; K.Omoda; S.Nagashima
    • US5437043, US5437043 Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers
      K.Fujii; N.Hamanaka; T.Tanaka; Y.Inagami; Y.Tamaki
    • 平07-066329, 昭61-286931, 昭60-128124, 平07-066329 情報処理装置
    • US5392443, US5392443 Vector processor with a memory assigned with skewed addresses adapted for concurrent fetching of a number of vector elements belonging to the same vector data
      T.Sakakibara; K.Kitai; Y.Inagami; Y.Tamaki; T.Tanaka; T.Isobe; S.Yazawa; M.Itoh
    • US5339396, US5339396 Interconnection network and crossbar switch for the same
      A.Muramatsu; K.Sakoda; I.Yoshihara; K.Nakao; M.Nohmi; N.Hamanaka; S.Nagashima; T.Tanaka
    • US5339429, US5339429 Parallel processing system and compiling method used therefor
      T.Tanaka; N.Hamanaka
    • US5301322, US5301322 System for converting job/process identifiers into processor/process identifiers in transferring data between processes in a multiprocessor system
      N.Hamanaka; T.Tanaka; K.Omoda; S.Nagashima
    • US5297255, US5297255 Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism
      N.Hamanaka; T.Tanaka
    • US5088034, US5088034 Compiling method for determining programs to be executed parallelly by respective processors in a parallel computer which transfer data with a data identifier to other processors
      S.Ihara; T.Tanaka; K.Iwasawa; N.Hamanaka
    • US5086498, US5086498 Parallel computer with asynchronous communication facility
      T.Tanaka; N.Hamanaka
    • US5043873, US5043873 Method of parallel processing for avoiding competition control problems and data up dating problems common in shared memory systems
      A.Muramatsu; K.Sakoda; I.Yoshihara; K.Nakao; M.Nohmi; N.Hamanaka; S.Nagashima; T.Tanaka
    • US5010477, US5010477 Method and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations
      K.Omoda; T.Tanaka. J.Nakagoshi; N.Hamanaka; S.Nagashima
    • US4985827, EP0301593A, US4985827, EP0301593A Computer for synchronized read and write of vector data
      N.Hamanaka; T.Tanaka; K.Omoda; J.Nakagoshi; K.Ojima; S.Nagashima
    • US4951193, EP258736, US4951193, EP258736 Computer for synchronized read and write of vector data
      A.Muramatsu; K.Sakoda; I.Yoshihara; K.Nakao; N.Hamanaka; S.Nagashima; T.Tanaka
    • US4918686, US4918686 Data transfer network suitable for use in a parallel computer
      T.Hayashi; K; Omoda; T.Tanaka. N.Hamanaka; S.Naashima
    • US4910667, US4910667 Vector processor with vector buffer memory for read or write of vector data between vector storage and operation unit
      T; Tanaka; K.Omoda; Y.Inagami; T.Nakagawa; M.Sugie; S.Nagashima
    • US4782441, US4782441 Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions
      Y.Inagami; S.Nagasima; K.Omoda; T.Nakagwa; T.Tanaka
    • US4782441 Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions
    • US4910667 Vector processor with vector buffer memory for read or write of vector data between vector storage and operation unit
    • US4918686 Data transfer network suitable for use in a parallel computer
    • US4951193, EP258736 Computer for synchronized read and write of vector data
    • US4985827, EP0301593A Computer for synchronized read and write of vector data
    • US5010477 Method and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations
    • US5043873 Method of parallel processing for avoiding competition control problems and data up dating problems common in shared memory systems
    • US5086498 Parallel computer with asynchronous communication facility
    • US5088034 Compiling method for determining programs to be executed parallelly by respective processors in a parallel computer which transfer data with a data identifier to other processors
    • US5297255 Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism
    • US5301322 System for converting job/process identifiers into processor/process identifiers in transferring data between processes in a multiprocessor system
    • US5339429 Parallel processing system and compiling method used therefor
    • US5339396 Interconnection network and crossbar switch for the same
    • US5392443 Vector processor with a memory assigned with skewed addresses adapted for concurrent fetching of a number of vector elements belonging to the same vector data
    • US5437043 Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers
    • US5465380, EP0255857 Data transfer method of transferring data between programs of a same program group in different processors using unique identifiers of the programs
    • US5506980Method and apparatus for parallel processing of a large data array utilizing a shared auxiliary memory
    • US5517619 Interconnection network and crossbar switch for the same
    • US5530881 Vector processing apparatus for processing different instruction set architectures corresponding to mingled-type programs and separate-type programs
    • US5590353 Data transfer method of transferring data between programs of a same program group in different processors using unique identifiers of the programs
    • US5710932, EP0326164B Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism
    • US5742766 Parallel computing system for synchronizing processors by using partial switch circuits for broadcasting messages after receiving synchronization signals and judging synchronization thereof
    • US5754876 Data processor system for preloading/poststoring data arrays processed by plural processors in a sharing manner
    • US5754792 Switch circuit comprised of logically split switches for parallel transfer of messages and a parallel processor system using the same
    • US5822605 Parallel processor system with a broadcast message serializing circuit provided within a network
    • US5826049 Partial broadcast method in parallel computer and a parallel computer suitable therefor
    • US5857110 Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors
    • US5867679, EP025865 Parallel processor system with asynchronous data transmission by a data producing processor to a data using processor employing controlled execution of a program by the data using processor for processing the data
    • US5892923 Parallel computer system using properties of messages to route them through an interconnect network and to select virtual channel circuits there within
    • US6298355 Computer system
    • US6321260 Media data communication method via network
    • US6510456 Data transfer control method and system, data transfer control program file, and file storage medium

    Social Contribution Activities

    • Apr. 2014 - 31 Mar. 2023
      一般社団法人IT産業懇話会 理事
      organizing_member

    Member History

    • Oct. 2014 - Jun. 2023
      理事
    • Apr. 1993 - Mar. 1996
      論文誌編集員
    • Apr. 1993 - Mar. 1995
      全国大会プログラム委員
    • Apr. 1990 - Mar. 1995
      アーキテクチャ研究会連絡員
    • Apr. 1990 - Mar. 1994
      JSPP90~JSPP94 プログラム委員
    • Apr. 1991 - Mar. 1992
      並列処理シンポジウムJSPP91 幹事