Kobayashi Ryotaro
| Faculty of Informatics Department of Computer Science | Professor |
Career
Affiliated academic society
IDs
Identifiers
研究者番号：40324454
researchmap会員ID：6000013956
ORCID ID：https://orcid.org/0000-0001-5956-3455
J-Global ID：200901051705888096
Paper
- A circuit for detecting IoT malware using signatures derived from processor information on LSI
Yutaro Matunaka; Kazuma Tachihana; Ryotaro Kobayashi; Masahiko Kato
International Journal of Information Security, 14 Jul. 2025, [Reviewed] - Real-time open-file backup system with machine-learning detection model for ransomware
Kosuke Higuchi; Ryotaro Kobayashi
International Journal of Information Security, 04 Jan. 2025, [Reviewed] - Updatable Decision Tree in Malware Detection Hardware Using Processor Information,
Issei Hayashi; Masahiko Kato; Ryotaro Kobayashi
The 11th International Workshop on Information and Communication Security (WICS 2024), Nov. 2024, [Reviewed] - Small-Scale Implementation of a Hardware Detector for Malicious Communications and Malware Targeting the IoT
Taku Sudo; Ryotaro Kobayashi; Masahiko Kato
The 11th International Workshop on Information and Communication Security (WICS 2024), Nov. 2024, [Reviewed] - Reducing Testing Time in Penetration Test Automation by Using EPSS and Parallelization
Kosei Okumura; Ryotaro Kobayashi
The 11th International Workshop on Information and Communication Security (WICS 2024), Nov. 2024, [Reviewed] - Hardware Mechanism for Detecting Malicious Communication in IoT Devices by using Time-Series Processor Information
Kyohei Fujiwara; Ryotaro Kobayashi; Masahiko Kato
The 12th International Symposium on Computing and Networking (CANDAR 2024), Nov. 2024, [Reviewed] - RanSMAP: Open dataset of Ransomware Storage and Memory Access Patterns for creating deep learning based ransomware detectors
Manabu Hirano; Ryotaro Kobayashi
Computers & Security, Nov. 2024, [Reviewed] - Poisoning Attacks against Network Intrusion Detection Systems Using Shapley values to Identify Trends in Poisoning Data
Tomohiro Hasegawa; Ryotaro Kobayashi
The 11th International Symposium on Computing and Networking (CANDAR 2023), Nov. 2023, [Reviewed] - Single-Hardware Method to Detect Malicious Communications and Malware on Resource-Constrained IoT Devices
Taku Sudo; Ryotaro Kobayashi; Masahiko Kato
The 10th International Workshop on Information and Communication Security (WICS 2023), Nov. 2023, [Reviewed] - Verification of IoT Malware Match Rate Using Signatures Created Based on Processor Information
Yutaro Matunaka; Ryotaro Kobayashi; Masahiko Kato
The 10th International Workshop on Information and Communication Security (WICS 2023), Nov. 2023, [Reviewed] - Real-Time Defense System using eBPF for Machine Learning-Based Ransomware Detection Method
Kosuke Higuchi; Ryotaro Kobayashi
The 10th International Workshop on Information and Communication Security (WICS 2023), Nov. 2023, [Reviewed] - FIMAR: Fast incremental memory acquisition and restoration system for temporal-dimension forensic analysis
Manabu Hirano; Ryotaro Kobayashi
Forensic Science International: Digital Investigation, Sep. 2023, [Reviewed] - Low Resource and Power Consumption and Improved Classification Accuracy for IoT Implementation of a Malware Detection Mechanism using Processor Information
Mutsuki Deguchi; Masahiko Katoh; Ryotaro Kobayashi
International Journal of Networking and Computing, Jul. 2023, [Reviewed] - Koga2022 Dataset: Comprehensive Dataset with Detailed Classification for Network Intrusion Detection Systems
Hideya Sato; Ryotaro Kobayashi
2022 Tenth International Symposium on Computing and Networking Workshops (CANDARW), Nov. 2022, [Reviewed] - Evaluation of Low-cost Operation of a Malware Detection Mechanism using Processor Information Targeting the IoT
Mutsuki Deguchi; Masahiko Katoh; Ryotaro Kobayashi
2022 Tenth International Symposium on Computing and Networking Workshops (CANDARW), Nov. 2022, [Reviewed] - Machine Learning-based Ransomware Detection Using Low-level Memory Access Patterns Obtained From Live-forensic Hypervisor
Manabu Hirano; Ryotaro Kobayashi
2022 IEEE International Conference on Cyber Security and Resilience (CSR), 27 Jul. 2022, [Reviewed] - Evaluation of implementability in a malware detection mechanism using processor information
Mutsuki Deguchi; Masahiko Katoh; Ryotaro Kobayashi
International Journal of Networking and Computing, Jul. 2022, [Reviewed]
Last - RanSAP: An open dataset of ransomware storage access patterns for training machine learning models
Manabu Hirano; Ryo Hodota; Ryotaro Kobayashi
Forensic Science International: Digital Investigation, Mar. 2022, [Reviewed] - IoT-oriented high-efficient anti-malware hardware focusing on time series metadata extractable from inside a processor core
Kazuki Koike; Ryotaro Kobayashi; Masahiko Katoh
International Journal of Information Security, 2022, [Reviewed] - A machine learning-based NIDS that collects training data from within the organization and updates the discriminator periodically and automatically,
Hideya Sato; Ryotaro Kobayashi
The 8th International Workshop on Information and Communication Security (WICS 2021), Nov. 2021, [Reviewed] - Evaluation of implementability in a malware detection mechanism using processor information
Mutsuki Deguchi; Masahiko Kato; Ryotaro Kobayashi
The 8th International Workshop on Information and Communication Security (WICS 2021), Nov. 2021, [Reviewed] - A prototype implementation and evaluation of the malware detection mechanism for IoT devices using the processor information
Hayate Takase; Ryotaro Kobayashi; Masahiko Kato; Ren Ohmura
International Journal of Information Security, Feb. 2020, [Reviewed] - Reduction of Classifier Size and Acceleration of Classification Algorithm in Malware Detection Mechanism using Processor Information
Kazuki Koike; Ryotaro Kobayashi; Masahiko Katoh
The 6th International Workshop on Information and Communication Security (WICS 2019), Nov. 2019, [Reviewed] - Machine Learning Based Ransomware Detection Using Storage Access Patterns Obtained From Live-forensic Hypervisor
Manabu Hirano; Ryotaro Kobayashi
The 6th IEEE International Conference on Internet of Things: Systems, Management and Security (IOTSMS 2019), Oct. 2019, [Reviewed] - Distributed Processing Framework for Machine Learning-based NIDS Construction
15 Sep. 2019, [Reviewed] - LogDrive: a proactive data collection and analysis framework for time-traveling forensic investigation in IaaS cloud environments
Manabu Hirano; Natsuki Tsuzuki; Seishiro Ikeda; Ryotaro Kobayashi
Journal of Cloud Computing, Dec. 2018, [Reviewed] - Cache Energy Reduction by Dynamically Switching The Highest-level Caches during Surplus Time Due to DVFS
齋藤 郁; 小林 良太郎; 嶋田 創
情報処理学会論文誌, 15 Mar. 2018, [Reviewed] - Forwarding path limitation and instruction allocation for in-order processor with ALU cascading
Ryotaro Kobayashi; Anri Suzuki; Hajime Shimada
Journal of Low Power Electronics and Applications, 01 Dec. 2017 - Detection and filtering system for DNS water torture attacks relying only on domain name information
Takuro Yoshida; Kento Kawakami; Ryotaro Kobayashi; Masahiko Kato; Masayuki Okada; Hiroyuki Kishimoto
Journal of Information Processing, 01 Sep. 2017, [Reviewed] - WaybackVisor: Hypervisor-based scalable live forensic architecture for timeline analysis
Manabu Hirano; Takuma Tsuzuki; Seishiro Ikeda; Naoga Taka; Kenji Fujiwara; Ryotaro Kobayashi
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2017, [Reviewed] - Improvement of Data Utilization Efficiency for Cache Memory by Compressing Frequent Bit Sequences
Ryotaro Kobayashi; Ikumi Kaneko; Hajime Shimada
IEICE TRANSACTIONS ON ELECTRONICS, Aug. 2016, [Reviewed] - Energy Reduction of BTB by Focusing on Number of Branches per Cache Line
Ryotaro Kobayashi; Kaoru Saito; Hajime Shimada
15 Apr. 2016 - A preliminary Study on Fine-Grained Heterogeneous Clustered Core
Anri Suzuki; Ikumi Kaneko; Ryotaro Kobayashi; Hajime Shimada
The 19th International Symposium on Low-Power and High-Speed Chips (COOLChips XIX), Apr. 2016, [Reviewed]
Corresponding - Reduction of Cache Energy by Switching between Ll High Speed and Low Speed Cache under application of DVFS
Kaoru Saito; Ryotaro Kobayashi; Hajime Shimada
2016 INTERNATIONAL CONFERENCE ON ADVANCED INFORMATICS - CONCEPTS, THEORY AND APPLICATION (ICAICTA), 2016, [Reviewed] - Instruction Rearrangement and Path Limitation for ALU Cascading
Anri Suzuki; Ryotaro Kobayashi; Hajime Shimada
2016 INTERNATIONAL CONFERENCE ON ADVANCED INFORMATICS - CONCEPTS, THEORY AND APPLICATION (ICAICTA), 2016, [Reviewed] - Defense method of HTTP GET flood attack by adaptively controlling server resources depending on different attack intensity
Ryotaro Kobayashi; Genki Otani; Takuro Yoshida; Masahiko Kato
Journal of Information Processing, 2016, [Reviewed] - Detection of the DNS Water Torture Attack by analyzing features of the subdomain name
Yuya Takeuchi; Takuro Yoshida; Ryotaro Kobayashi; Masahiko Kato; Hiroyuki Kishimoto
Journal of Information Processing, 2016, [Reviewed] - Energy reduction of BTB by focusing on number of branches per cache line
Ryotaro Kobayashi; Kaoru Saito; Hajime Shimada
Journal of Information Processing, 2016, [Reviewed] - HTTP-GET Flood Prevention Method by Dynamically Controlling Multiple Types of Virtual Machine Resources
Mizuki Watanabe; Ryotaro Kobayashi; Masahiko Kato
15 Sep. 2015 - HTTP-GET flood prevention method by dynamically controlling multiple types of virtual machine resources
Mizuki Watanabe; Ryotaro Kobayashi; Masahiko Kato
Journal of Information Processing, 15 Sep. 2015, [Reviewed] - BTB Energy Reduction by Focusing on Useless Accesses
Yoshio Shimomura; Hiroki Yamamoto; Hayato Usui; Ryotaro Kobayashi; Hajime Shimada
IEICE TRANSACTIONS ON ELECTRONICS, Jul. 2015, [Reviewed] - Reducing Cache Hardware by Focusing on Data Redundancy
Ryotaro Kobayashi; Daisuke Matsukawa; Yoshio Shimomura; Hiroya Ochiai; Hajime Shimada
ELECTRONICS AND COMMUNICATIONS IN JAPAN, Sep. 2014, [Reviewed] - Reducing cache hardware by focusing on data redundancy
Ryotaro Kobayashi; Daisuke Matsukawa; Yoshio Shimomura; Hiroya Ochiai; Hajime Shimada
IEEJ Transactions on Electronics, Information and Systems, 2013 - A stride value predictor suppressing conflicts focusing on predictability
Yoshio Shimomura; Ryotaro Kobayashi
ELECTRONICS AND COMMUNICATIONS IN JAPAN, May 2012, [Reviewed] - Energy saving of value prediction by expanding branch target buffer
Yoshio Shimomura; Ryotaro Kobayashi
IEEJ Transactions on Electronics, Information and Systems, 2012 - HTTP-GET Flood Provision by Dynamic Resource Control of Virtual Machine
TAKAHASHI Tomohide; TAGUCHI Genki; KOBAYASHI Ryotaro; KATOH Masahiko
The IEICE transactions on information and systems (Japanese edetion), 01 Dec. 2011 - A stride value predictor suppressing conflicts focusing on predictability
Yoshio Shimomura; Ryotaro Kobayashi
IEEJ Transactions on Electronics, Information and Systems, 2011 - Slack Sharing Based on Dependences
KOBAYASHI Ryotaro; TANIGUCHI Hideki; ICHIKAWA Akitaka; SHIMADA Toshio
The IEICE transactions on information and systems (Japanese edetion), 01 Jun. 2008 - Power consumption reduction scheme focusing on the depth of speculative execution
Hideki Oshima; Ryotaro Kobayashi; Kazuki Shimura; Toshio Shimada
2008 IEEE 8TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION TECHNOLOGY, VOLS 1 AND 2, 2008, [Reviewed] - A novel low-power processor with variable pipeline control
Toshio Shimada; Tadahiro Madokoro; Hideki Oshima; Ryotaro Kobayashi
2008 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, 2008, [Reviewed] - Local Slack Predictor Based on Heuristics(Processor Architecture)
KOBAYASHI RYOTARO; HAYASHI HISAHIRO; SHIMADA TOSHIO
情報処理学会論文誌コンピューティングシステム（ACS）, 15 Sep. 2006 - Limits of Thread-Level Parallelism in Non-numerical Programs
Akio Nakajima; Ryotaro Kobayashi; Hideki Ando; Toshio Shimada
15 May 2006 - Limits of Thread-Level Parallelism in Non-numerical Programs(System Evaluation)
NAKAJIMA AKIO; KOBAYASHI RYOTARO; ANDO HIDEKI; SHIMADA TOSHIO
情報処理学会論文誌. コンピューティングシステム, 15 May 2006 - Limits of Thread-Level Parallelism in Non-numerical Programs
Nakajima Akio; Kobayashi Ryotaro; Ando Hideki; Shimada Toshio
ipsjdc, 2006 - A Preactivating Mechanism for Supperssing the Performance Degradation in a VT-CMOS Cache Using Address Prediction(Cashe Mechanism)
KOBAYASHI RYOTARO; FUJIOKA RYO; ANDO HIDEKI; SHIMADA TOSHIO
情報処理学会論文誌コンピューティングシステム（ACS）, 15 Jan. 2005 - A Sharing Scheme of Physical Registers by Exploiting Frequent Values
YAMAMOTO AKIHIRO; OKUMA MINORU; KATAYAMA KIYOKAZU; KOBAYASHI RYOTARO; ANDO HIDEKI; SHIMADA TOSHIO
情報処理学会論文誌コンピューティングシステム（ACS）, 15 Oct. 2004, [Reviewed] - A Multiprocessor Architecutre SKY that Exploits Thread-Level Parallelism in Non-Numerical Applications (Special Issue on Multimedia Network System)
KOBAYASHI RYOTARO; OGAWA YUKIHIRO; IWATA MITSUAKI; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ Journal, 15 Feb. 2001 - A Branch Target Buffer with a Two-level Table Scheme(Special Issue on Parallel Processing)
KOBAYASHI RYOTARO; YAMADA YUJI; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ Journal, 15 May 2000 - Branch Predictor Design Using Genetic Algorithm
NOGUCHI Ryota; MATSUZAKI Motoaki; KOBAYASHI Ryotaro; ANDO Hideki; SHIMADA Toshio
計測自動制御学会論文集, 30 Nov. 1999 - A Branch Prediction Scheme that Reduces Destructive Aliasing Using Branch Direction Bias (Special Issue on Parallel Processings)
NOGUCHI RYOTA; MORI ATSUSHI; KOBAYASHI RYOTARO; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ Journal, 15 May 1999
Lectures, oral presentations, etc.
- ハイパーバイザで収集したメモリ，ストレージ，ネットワークの振る舞い特徴量を用いた二重脅迫型ランサムウェア検知システム,
31 Jan. 2025 - 深層学習を用いたランサムウェア検知システムに対する振る舞い変化を用いた回避攻撃とその対策
31 Jan. 2025 - Building an Automated Deobfuscation System that Integrates Multiple Deobfuscation Tools
Kohei Arai; Ryotaro Kobayashi
The 15th International Workshop on Networking, Computing, Systems, and Software (NCSS 2024), 28 Nov. 2024 - Peer Tutoring型CTF「kogaCTF」で出題した問題の特徴と解説
23 Oct. 2024 - ハードウェアベースでのマルウェア検知におけるbit分割と幅削減による分類器のサイズと生成時間の削減
Oct. 2024 - 自動表層解析システムにおけるFFRI Dataset scriptsの利用と拡張
Oct. 2024 - Rustで生成されたマルウェアを解析するためのGhidra拡張機能の開発
Oct. 2024 - 攻撃トラフィック量に動的に対応する機械学習ベースのFPGAを用いたNIPS
Oct. 2024 - kogaCTFを活用した情報セキュリティ教育へのPeer Tutoringの導入による学習効果の検討
Oct. 2024 - 準パススルー型ハイパーバイザによるCPUの振る舞い特徴量の収集とサイバー攻撃の検知
Aug. 2024 - 二重脅迫型ランサムウェアの攻撃シナリオ再現システムと振る舞い特徴量データセットの構築
Aug. 2024 - 敵対的生成ネットワークを用いた標的型回避攻撃の 振る舞い型ランサムウェア検知システムへの適用
Jan. 2024 - ストレージとメモリのアクセスパターンを用いた振る舞い型 ランサムウェア検知システム： ハードウェアの違いが与える影響の分析
Jan. 2024 - 組織内ネットワークに対する自動ぺネトレーションツールの作成とその評価
Oct. 2023 - プロセッサ情報の平均特徴量および空間特徴量を用いた悪性通信を検出する機構の評価
Oct. 2023 - 多種多様なマルウェアに対する自動表層解析システムの提案
Oct. 2023 - 準パススルー型ハイパーバイザを用いたネットワーク監視機能の実装
Aug. 2023 - 機械学習を用いたランサムウェア検知におけるメモリとストレージのアクセスパターンの特徴重要度の分析
Dec. 2022 - ストレージとメモリのアクセス速度の違いを考慮した深層学習によるランサムウェア検知システム
Dec. 2022 - NIDS に対する中毒攻撃に関する調査及び詳細把握のための評価指標の導入
Oct. 2022 - プロセッサ情報を用いたマルウェア検知機構におけるバージョン互換性有無の評価,
Oct. 2022 - 準パススルー型ハイパーバイザーを用いた差分メモリダンプ機構の評価
Jul. 2022 - 準パススルー型ハイパーバイザを用いて取得したメモリデータの分析
Jan. 2022 - 深層学習によるディスクアクセスパターンを用いたランサムウェア検知システム
Oct. 2021 - 準パススルー型ハイパーバイザを用いたOSごとのメモリアクセスパターンの違いの調査
Sep. 2021 - 組織内で学習データを採取し定期的に判別器を更新する機械学習ベースのNIDS
Mar. 2021 - ストレージアクセスパターンを用いた機械学習によるランサムウェア判別システムの精度向上に関する考察
Mar. 2021 - デコイファイルを用いた暗号化型ランサムウェアの検知とプロセス特定に関する検討
Mar. 2021 - 準パススルー型ハイパーバイザによるメモリデータ収集機能の性能改善と評価
Mar. 2021 - 機械学習ベースのNIDSにおける動的な判別器生成に関する検討と予備評価
Nov. 2020 - 3D画像識別によるマルウェア検知を目的としたプログラムの挙動の可視化に関する検討
Nov. 2020 - 組織内ネットワークにおけるハニーポットを備えた動的な機械学習ベースのNIDSの作成と予備的評価
Oct. 2020 - プロセッサ情報を用いたマルウェア検知機構のFPGA実装のための予備評価
Oct. 2020 - ダミーファイルを用いた暗号化型ランサムウェアの検出と防御に関する検討
Oct. 2020 - 準パススルー型ハイパーバイザーを用いた時系列メモリデータ取得機能の試作と評価
Mar. 2020 - ストレージアクセスパターンに着目した機械学習及び深層学習によるランサムウェアの検知手法の検討
Mar. 2020 - 画像処理ベースのプログラム識別を目的としたプログラムの挙動の可視化に関する検討
Dec. 2019 - ダミーファイルを利用した暗号型ランサムウェア対策システムの実装
Oct. 2019 - プロセッサ情報によるマルウェア検知における特徴量のビット数削減手法の検討
Oct. 2019 - ストレージアクセスパターンと機械学習を用いたランサムウェアの検知システム
Sep. 2019 - 準パススルー型ハイパーバイザーを用いたメモリフォレンジックの提案
Sep. 2019 - プロセッサ情報を用いたマルウェア検知におけるアルゴリズムの高速化の検討
Mar. 2019 - プログラムカウンタのアドレス空間の履歴に着目したCNNによるマルウェア検知
Dec. 2018 - プロセッサ情報を用いたマルウェア検知機構における分類器のサイズ削減手法の検討
Dec. 2018 - ストレージアクセス履歴の時系列解析システムの実装とランサムウェア解析への応用
Dec. 2018 - Windowsにおけるプロセッサレベルの特徴量に着目した亜種マルウェアの検知
Oct. 2018 - 準パススルー型ハイパーバイザによる ストレージアクセスパターンの収集システムの提案
Oct. 2018 - RISC-Vにおけるプロセッサ情報を用いた動的なアノマリ検知機構
Oct. 2018 - プロセッサレベルの特徴量に着目した亜種マルウェアの検知
Mar. 2018 - Preliminary Evaluation on the Program Classification at the Processor Level using Machine Learning
小林 良太郎; 高瀬 誉; 大谷 元輝; 大村 廉; 加藤 雅彦
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 20 Nov. 2017, 電子情報通信学会 - 準パススルー型ハイパーバイザを用いたランサムウェアのディスクアクセスパターン解析に向けた取り組み
池田征士朗; 都築夏樹; 藤原賢二; 平野学; 小林良太郎
電気・電子・情報関係学会東海支部連合大会講演論文集(CD-ROM), 28 Aug. 2017 - 準パススルー型ハイパーバイザによるストレージ装置の読み書き監視システム
高直我; 都築卓馬; 藤原賢二; 平野学; 小林良太郎
電気・電子・情報関係学会東海支部連合大会講演論文集(CD-ROM), 28 Aug. 2017 - Discussion and Evaluation on Regeneration of New Kyoto 2006+ Data Set
多田 竜之介; 小林 良太郎; 嶋田 創; 高倉 弘喜
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 25 Nov. 2016, 電子情報通信学会 - Study on Filtering Method for the DNS Water Torture Attack Utilizing the Naive Bayes Classifier
吉田 琢朗; 竹内 優也; 小林 良太郎; 加藤 雅彦; 岸本 裕之
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 14 Jul. 2016, 電子情報通信学会 - Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment
齋藤 郁; 小林 良太郎; 嶋田 創
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 01 Dec. 2015, 電子情報通信学会 - 細粒度なヘテロジニアスクラスタコアによる消費電力削減の提案
KANEKO IKUMI; KOBAYASHI RYOTARO; SHIMADA HAJIME
情報処理学会全国大会講演論文集, 17 Mar. 2015 - 頻出ビット列の圧縮によるキャッシュメモリのデータ利用効率の向上
OCHIAI HIROYA; KOBAYASHI RYOTARO; SHIMADA HAJIME
情報処理学会全国大会講演論文集, 17 Mar. 2015 - Energy Reduction of BTB by focusing on Number of Branches per Cache Line
YAMAMOTO Hiroki; KOBAYASHI Ryotaro; SHIMADA Hajime
IEICE technical report. Computer systems, 06 Mar. 2015, The Institute of Electronics, Information and Communication Engineers - Energy Reduction of BTB by focusing on Number of Branches per Cache Line
27 Feb. 2015, Information Processing Society of Japan (IPSJ) - Study of Processor Core for Many-core Architecture Combining ALU Cascading and 3-way In-order Execution
SHIMADA Hajime; KOBAYASHI Ryotaro
IEICE technical report. Computer systems, 10 Oct. 2014, The Institute of Electronics, Information and Communication Engineers - DVFS使用時におけるFilter Bufferを用いたキャッシュの消費電力削減
KONDO MASAHIRO; OCHIAI HIROYA; KOBAYASHI RYOTARO
電気・電子・情報関係学会東海支部連合大会講演論文集(CD-ROM), 01 Sep. 2014 - Low Energy Consumption Oriented Heterogeneous Clustered Processor by Renewing A Part of Register Value
KAWAI Shoma; KOBAYASHI Ryotaro; SHIMADA Hajime
IEICE technical report. Computer systems, 08 Nov. 2013, The Institute of Electronics, Information and Communication Engineers - Evaluation of a Dependable Interrupt Interface by Bundled Interrupt Request Lines
NOMURA Hayato; SHIMADA Hajime; KOBAYASHI Ryotaro
IEICE technical report. Computer systems, 08 Nov. 2013, The Institute of Electronics, Information and Communication Engineers - 無駄な参照に着目し,BTBの消費エネルギーを削減する研究
YAMAMOTO HIROKI; USUI HAYATO; SHIMOMURA YOSHIO; KOBAYASHI RYOTARO
電気関係学会東海支部連合大会講演論文集(CD-ROM), 18 Sep. 2012 - L-032 HTTP-GET Flood Prevention by Using Multiple Decoy Machines
Yoshida Shoma Mikami; Yoshida Shoma Mikami; Yoshida Shoma Mikami; Yoshida Shoma Mikami; Yoshida Shoma Mikami
情報科学技術フォーラム講演論文集, 04 Sep. 2012, FIT(電子情報通信学会・情報処理学会)運営委員会 - M-006 Scheduling of Clients in Internet Reservation System Using Temporary Access Right
Mikami Tsuyoshi; Yoshida Shoma; Kobayashi Ryotaro; Kato Masahiko; Kanaoka Akira
情報科学技術フォーラム講演論文集, 04 Sep. 2012, FIT(電子情報通信学会・情報処理学会)運営委員会 - Education of Semiconductor and Integrated Circuit Engineering by IC Layout and IC Manufacture
Akiyama Masahiro; Karasawa Koichi; Ohira Yusuke; Kobayashi Ryotaro
Japanese colleges of technology education journal, Mar. 2012, Institute of National Colleges of Technology,Japan - A Memory Objects Allocation Scheme to Improve Soft Errors Tolerance on Embedded Systems with a Scratch-pad Memory
森本 喬; 小林 良太郎; 杉原 真
組込みシステムシンポジウム2011論文集, 12 Oct. 2011 - C-002 A Study on Reduction of Execution Phases Based on Pre-Execution
Shimomura Yoshio; Kobayashi Ryotaro
情報科学技術フォーラム講演論文集, 07 Sep. 2011, FIT(電子情報通信学会・情報処理学会)運営委員会 - ポートの利用率に着目したオンチップルータにおける入力バッファ共有化
02 Mar. 2011 - 半導体素子の製作プロセス学習支援
27 Aug. 2010 - レイアウトエディタを用いた半導体素子設計による技術者育成 : 演算増幅回路製作同好会学生教育用
30 Jun. 2010 - Memory Dependence Prediction and Synchronization on Multi-core processor
Koji Akita; Ryotaro Kobayashi; Hideki Ando
IPSJ SIG Notes, 22 Feb. 2010, 一般社団法人情報処理学会 - An Implementation and Evaluation of Software Memory Management for Feature-Packing
Takefumi Miysohi; Masaru Iritani; Koh Uehara; Koichi Sasada; Ryotaro Kobayashi; Kenji Kise
IPSJ SIG Notes, 21 Jan. 2010, 一般社団法人情報処理学会 - レイアウトソフトを使った半導体工学教育実践
27 Aug. 2009 - C-005 Efficiency improvement of Value Prediction with Learning-Table
Shimomura Yoshio; Kobayashi Ryotaro
20 Aug. 2009, Forum on Information Technology - C-004 Main Memory Access Latency Tolerance in Write Back Cache
Shimomura Yoshio; Kobayashi Ryotaro
情報科学技術フォーラム講演論文集, 20 Aug. 2009, FIT(電子情報通信学会・情報処理学会)運営委員会 - C-021 A Fast Packet Forwarding Mechanism for Virtual Router
Taguchi Genki; Kobayashi Ryotaro; Hirotsu Toshio
情報科学技術フォーラム講演論文集, 20 Aug. 2009, FIT(電子情報通信学会・情報処理学会)運営委員会 - C-034 Investigation of Soft Error Correction Mechanism Focused on Flip-Flop
Muneoka Tomonari; Kobayashi Ryotaro
情報科学技術フォーラム講演論文集, 20 Aug. 2009, FIT(電子情報通信学会・情報処理学会)運営委員会 - C-001 A Study of Optimum Core Allocation for Uniting Core Architecture
Yamada Yusuke; Kobayashi Ryotaro; Wakasugi Yuhta; Kise Kenji
情報科学技術フォーラム講演論文集, 20 Aug. 2009, FIT(電子情報通信学会・情報処理学会)運営委員会 - C-002 Preliminary Evaluation on Adaptable Data Access Support for Manycore
Takahashi Tomohide; Kobayashi Ryotaro; Kise Kenji
情報科学技術フォーラム講演論文集, 20 Aug. 2009, FIT(電子情報通信学会・情報処理学会)運営委員会 - Memory Management for Feature-Packing by Compiler
MIYOSHI TAKEFUMI; SASADA KOICHI; KOBAYASHI RYOTARO; UEHARA KOH; KISE KENJI
IPSJ SIG Notes, 12 Oct. 2008, 一般社団法人情報処理学会 - Development of Simple and Effective Many-Core Architecture
UEHARA KOH; SATO SHIMPEI; MORIYA AKIRA; FUJIEDA NAOKI; TAKAMAEDA SHINYA; WATANABE SHIMPEI; MIYOSHI TAKEFUMI; KOBAYASHI RYOTARO; KISE KENJI
IPSJ SIG Notes, 12 Oct. 2008, 一般社団法人情報処理学会 - A Challenge for Systems Software in the era of Many Core Processors
SASADA KOICHI; MIYOSHI TAKEFUMI; KOBAYASHI RYOTARO; KISE KENJI
IPSJ SIG Notes, 16 Apr. 2008, 一般社団法人情報処理学会 - Feature-Packing : Architectural-level Techniques for Multifunction Many-core
KOBAYASHI RYOTARO; KISE KENJI
IPSJ SIG Notes, 21 Nov. 2007, 一般社団法人情報処理学会 - A low power consumption processor with on-chip control mechanism using pipeline stage unification
KIMURA Katsuya; KOBAYASHI Ryotaro; SHIMADA Toshio
IEICE technical report, 14 Nov. 2007, 一般社団法人電子情報通信学会 - A Study on Control Scheme of Awake Time in Drowsy Caches
KOBAYASHI Ryotaro; TANIGUCHI Hideki; SHIMADA Toshio
IPSJ SIG Notes, 31 May 2007, 一般社団法人情報処理学会 - A Study on Control Scheme of Awake Time in Drowsy Caches
KOBAYASHI Ryotaro; TANIGUCHI Hideki; SHIMADA Toshio
IEICE technical report, 24 May 2007, The Institute of Electronics, Information and Communication Engineers - Discussion about Technique for Speculatively Switching Context by Predicting Task
NAGATA MASATOSHI; KOBAYASHI RYOTARO; SHIMADA TOSHIO
IPSJ SIG Notes, 05 Apr. 2007, 一般社団法人情報処理学会 - Slack Sharing Technique for Increasing the Number of Slack Instructions
KOBAYASHI RYOTARO; ICHIKAWA AKITAKA; SHIMADA TOSHIO
IPSJ SIG Notes, 01 Mar. 2007, 一般社団法人情報処理学会 - On-Chip Control Mechanisms for Pipeline Stage Unification
MADOKORO TAKAHIRO; KOBAYASHI RYOTARO; SHIMADA TOSHIO
IPSJ SIG Notes, 01 Mar. 2007, 一般社団法人情報処理学会 - Power Consumption Reduction Scheme Focusing on the Depth of Speculative Execution
KOBAYASHI RYOTARO; SHIMURA KAZUKI; SHIMADA TOSHIO
IPSJ SIG Notes, 01 Mar. 2007, 一般社団法人情報処理学会 - Slack Sharing Technique for Increasing the Number of Slack Instructions
KOBAYASHI RYOTARO; ICHIKAWA AKITAKA; SHIMADA TOSHIO
IPSJ SIG Notes, 01 Mar. 2007, 一般社団法人情報処理学会 - On-Chip Control Mechanisms for Pipeline Stage Unification
MADOKORO TAKAHIRO; KOBAYASHI RYOTARO; SHIMADA TOSHIO
IPSJ SIG Notes, 01 Mar. 2007, 一般社団法人情報処理学会 - Local Slack Predictor Focusing on Dynamic Behavior of Instructions
KOBAYASHI Ryotaro; HAYASHI Hisahiro; SHIMADA Toshio
16 Mar. 2006, Information Processing Society of Japan (IPSJ) - Local Slack Predictor Focusing on Dynamic Behavior of Instructions
KOBAYASHI Ryotaro; HAYASHI Hisahiro; SHIMADA Toshio
IEICE technical report. Computer systems, 09 Mar. 2006, 一般社団法人電子情報通信学会 - Usage of Register Cache Focusing on Critical Path
KOBAYASHI RYOTARO; KAJIYAMA TARO; SHIMADA TOSHIO
IPSJ SIG Notes, 27 Feb. 2006, 一般社団法人情報処理学会 - High Accuracy of Register Cache with Ordering of Physical Register Number
KOBAYASHI RYOTARO; HORIBE DAISUKE; SHIMADA TOSHIO
IPSJ SIG Notes, 27 Feb. 2006, 一般社団法人情報処理学会 - An LSI design to support Sound Finite Difference Time Domain Method
ITO Daichi; KOBAYASHI Ryotaro; SHIMADA Toshio
IEICE technical report. Computer systems, 10 Jan. 2006, 一般社団法人電子情報通信学会 - Performance Evaluation of Speculative Thread Execution in the Single-Chip Multiprocessor SKY
KAMIMURAI Akio; KOBAYASHI Ryotaro; ANDO Hideki; SHIMADA Toshio
26 Jan. 2005, Information Processing Society of Japan (IPSJ) - Performance Evaluation of Speculative Thread Execution in the Single-Chip Multiprocessor SKY
KAMIMURAI Akio; KOBAYASHI Ryotaro; ANDO Hideki; SHIMADA Toshio
IEICE technical report. Computer systems, 19 Jan. 2005, 一般社団法人電子情報通信学会 - A Physical Register Sharing Technique for an SMT Processor Implementing the Multithread Model of the SKY
SHIBUYA MAHO; KOBAYASHI RYOTARO; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ SIG Notes, 01 Dec. 2004, 一般社団法人情報処理学会 - A Dataflow-based Thread Partitioning Technique in a Single-Chip Multiprocessor SKY
YAMAGUCHI TAKESHI; KOBAYASHI RYOTARO; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ SIG Notes, 02 Feb. 2004, 一般社団法人情報処理学会 - Limits of Thread-Level Parallelism in Non-Numerical Programs : Relation with Inter-Thread Memory Disambiguation Techniques
NAKAJIMA AKIO; KOBAYASHI RYOTARO; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ SIG Notes, 02 Feb. 2004, 一般社団法人情報処理学会 - Reducing Physical Registers with Sharing Techniques by Exploiting Recent-Value Locality
OKUMA MINORU; KATAYAMA KIYOKAZU; KOBAYASHI RYOTARO; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ SIG Notes, 22 Aug. 2002, 一般社団法人情報処理学会 - Evaluation of a Thread Partitioning Techniques in a Single-Chip Multiprocessor Architecture SKY
Kawaume Yoshinori; Kobayashi Ryotaro; Ando Hideki; Shimada Toshio
IPSJ SIG Notes, 01 Feb. 2002, Information Processing Society of Japan (IPSJ) - Evaluation of Memory Synchronization Mechanisms in a Single-Chip Multiprocessor Architecture SKY
Ichimura Kazuhito; Kobayashi Ryotaro; Ando Hideki; Shimada Toshio
IPSJ SIG Notes, 01 Feb. 2002, 一般社団法人情報処理学会 - A preactivating mechanism for a VT-CMOS cache using address prediction
R Fujioka; K Katayama; R Kobayashi; H Ando; T Shimada
ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2002 - A Technique to Suppress Performance Degradation on VT-CMOS Data Cache using Address Prediction
FUJIOKA Ryo; KATAYAMA Kiyokazu; KOBAYASHI Ryotaro; ANDO Hideki; SHIMADA Toshio
Technical report of IEICE. ICD, 19 Oct. 2001, 一般社団法人電子情報通信学会 - A Multiprocessor Architecture SKY that Exploits Thread-Level Parallelism in Non-Numerical Applications
KOBAYASHI Ryotaro; OGAWA Yukihiro; IWATA Mitsuaki; ANDO Hideki; SHIMADA Toshio
Transactions of Information Processing Society of Japan, 2001, Information Processing Society of Japan (IPSJ) - Limits of Thread-Level Parallelism in Non-Numerical
Kanou Masaaki; Kobayashi Ryotaro; Ando Hideki; Shimada Toshio
IPSJ SIG Notes, 29 Nov. 2000, 一般社団法人情報処理学会 - Evaluation of an On-Chip Multiprocessor Architecture SKY
OGAWA Yukihiro; KOBAYASHI Ryotaro; ANDO Hideki; SHIMADA Toshio
Technical report of IEICE. VLD, 26 Nov. 1999, The Institute of Electronics, Information and Communication Engineers - Evaluation of an On-Chip Multiprocessor Architecture SKY
Ogawa Yukihiro; Kobayashi Ryotaro; Ando Hideki; Shimada Toshio
IPSJ SIG Notes, 26 Nov. 1999, 一般社団法人情報処理学会 - Instruction-Issue Mechanism for a Clustered Superscalar Processor Focusing on a Critical Path in Data Flow Graph
KOBAYASHI RYOTARO; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ SIG Notes, 02 Aug. 1999, 一般社団法人情報処理学会 - A Branch Prediction Scheme that Reduces Destructive Aliasing Using Branch Direction Bias
NOGUCHI Ryota; MORI Atsushi; KOBAYASHI Ryotaro; ANDO Hideki; SHIMADA Toshio
Transactions of Information Processing Society of Japan, 15 May 1999, Information Processing Society of Japan (IPSJ) - An on-chip multiprocessor architecture with a non-blocking synchronization mechanism
Ryotaro Kobayashi; Mitsuaki Iwata; Yukihiro Ogawa; Hideki Ando; Toshio Shimada
Conference Proceedings of the EUROMICRO, 1999, IEEE Computer Society - Branch Predictor Design Using Genetic Algorithm
NOGUCHI Ryota; MATSUZAKI Motoaki; KOBAYASHI Ryotaro; ANDO Hideki; SHIMADA Toshio
Transactions of the Society of Instrument and Control Engineers, 1999, The Society of Instrument and Control Engineers - A Study on Branch Predictors that Dynamically Reduce Destructive Aliasings
MORI ATSUSHI; KOBAYASHI RYOTAROU; ANDO HIDEKI; SHIMADA TOSHIO
IEICE technical report. Computer systems, 15 Oct. 1998, 一般社団法人電子情報通信学会 - Reducing the Amount of Branch Target Buffers with a 2-Level Table Scheme, Utilizing the Characteristics of Branch Target Addresses
YAMADA YUJI; KOBAYASHI RYOTARO; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ SIG Notes, 21 Sep. 1998, 一般社団法人情報処理学会 - A Thread Partitioning Technique that Utilizes Control Equivalence
IWATA MITSUAKI; KOBAYASHI RYOTARO; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ SIG Notes, 05 Mar. 1998, 一般社団法人情報処理学会 - Branch Predictor Design Using Genetic Algorithm
Noguchi Ryouta; Matsuzaki Motoaki; Kobayasi Ryoutarou; Ando Hideki; Shimada Toshio
IEICE technical report. Computer systems, 30 Jan. 1998, 一般社団法人電子情報通信学会 - Branch Prediction Scheme with Reducing Destructive Aliasing
NOGUCHI RYOUTA; MORI ATSUSI; KOBAYASI RYOUTAROU; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ SIG Notes, 11 Dec. 1997, 一般社団法人情報処理学会 - Hybrid Branch Predictor Design Based on Orthogonality
MORI ATSUSHI; KOBAYASHI RYOTAROU; NOGUCHI RYOTA; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ SIG Notes, 20 Aug. 1997, 一般社団法人情報処理学会 - A Proposal and preliminary evaluation of a speculative execution Mechanism with control dependence analysis and multiple instruction flow execution
KOBAYASHI RYOTARO; IWATA MITSUAKI; ANDO HIDEKI; SHIMADA TOSHIO
IPSJ SIG Notes, 20 Aug. 1997, 一般社団法人情報処理学会
Award
- Nov. 2024
Reducing Testing Time in Penetration Test Automation by Using EPSS and Parallelization
The 11th International Workshop on Information and Communication Security (WICS 2024), WICS Best Paper Award
Kosei Okumura;Ryotaro Kobayashi - Oct. 2021
準パススルー型ハイパーバイザによるメモリデータ収集機能の性能改善と評価 - May 2021
工学院大学「情報学部寄附講義の取組みと成果」 - Oct. 2019
プロセッサ情報を用いたマルウェア検知機構における分類器のサイズ削減手法の検討 - Sep. 2017
NIDS評価用データセット：Kyoto 2016 Datasetの作成 - May 2002
非数値計算応用向けスレッド・レベル並列処理マルチプロセッサ・アーキテクチャSKY - Sep. 1999
非数値計算プログラムのスレッド間命令レベル並列を利用するプロセッサ・アーキテクチャSKY
Research Themes
- 01 Apr. 2023 - 31 Mar. 2027
Counter APT operation with detection involving attacks to ML based security system
Grant-in-Aid for Scientific Research (B), Nagoya University - 01 Apr. 2023 - 31 Mar. 2027
Detection and Meeasure for APT Involving Attack to ML Security Systems
Grant-in-Aid for Scientific Research (B), Nagoya University - 01 Apr. 2023 - 31 Mar. 2027
Hypervisor-based Evidence Preservation Forensic System against Double Extortion Ransomware
Grant-in-Aid for Scientific Research (C), National Institute of Technology, Toyota College - 01 Apr. 2019 - 31 Mar. 2023
Countermeasure for counter machine/deep learning based detection system types of malware exploitation
Grant-in-Aid for Scientific Research (B), Nagoya University - 01 Apr. 2017 - 31 Mar. 2021
Hypervisor-based digital forensic evidence preservation system and its application to machine learning
Grant-in-Aid for Scientific Research (C), National Institute of Technology, Toyota College - 01 Apr. 2017 - 31 Mar. 2020
High efficiency IoT many-core for security acceleration
Grant-in-Aid for Scientific Research (C), Kogakuin University - 01 Apr. 2016 - 31 Mar. 2019
Computer system which improves both throughput and power performance ratio for counter cyber attack algorithmsh
Grant-in-Aid for Scientific Research (C), Nagoya University - 01 Apr. 2014 - 31 Mar. 2017
Many-core Processor Implemented by Clustered-Core Including Clusters of Different Power
Grant-in-Aid for Scientific Research (C), Toyohashi University of Technology - 01 Apr. 2013 - 31 Mar. 2016
A processor core for many-core with fine grained PSU and ALU cascading control
Grant-in-Aid for Scientific Research (C), Nagoya University - 2009 - 2010
Cooperative Cores for Manycore Processor
Grant-in-Aid for Young Scientists (B), Toyohashi University of Technology - 1999 - 2001
Research on Branch Prediction and Speculative Execution
Grant-in-Aid for Scientific Research (C), Nagoya University - 1995 - Present
並列処理技術による計算機システムの高速化，省電力化，高信頼化
